Hello FPGAmigos,

My name is Théophile Loubiere. I am a junior FPGA engineer from France with “3” years of experience. The “3” is in quotes because I sometimes grapple with impostor syndrome. I don’t feel entirely comfortable claiming to be an FPGA engineer with three years of experience. I left my previous job because I felt I wasn’t learning quickly enough, and the projects I was involved in were contributing to some of society’s major problems (Defense = war; aviation, cars, telecom = pollution). This blog is my response to both of those issues.

Firstly, by actively seeking new FPGA knowledge, cross-referencing sources, applying this knowledge in projects, and sharing it with you through articles, I believe I will acquire more skills and gain a deeper understanding of the subjects than I would in a role where I’m merely a verification engineer without access to (or time for) the design source code. My hope is that this blog will serve as a repository of concentrated knowledge that will help you improve your skills, excel in your job, earn a promotion, buy a house, find a partner, start a family, or even conquer the world.

Secondly, I aim to work on projects that are meaningful and beneficial to humanity without causing harm to our planet or its inhabitants. For instance, I’d rather work on a bird/insect recognition neural network to identify species than on thermal recognition to target individuals in the dark. Don’t worry, I’m not skilled enough to do that… yet 😉

So, what can you expect to find on this blog? (Please let me know in the comments what you’re most interested in.)

1. FPGA hardware

One of the key insights I’ve gained is that designing an FPGA requires more than just knowledge of RTL languages. A deep understanding of your hardware’s inner workings is crucial for the success of your final project. That’s why I plan to research every component inside an FPGA and share my findings with you.

2. RTL languages

What should we learn? VHDL? Verilog? SystemVerilog? HLS? Or perhaps an obscure open-source language that no one uses? Let’s explore them and find out. I’m not sure which is the best…

3. Verification

I have a hunch about this one: test benches are software and should be written in General Purpose Languages (GPL) like Python, C, C++, Rust, etc., not in VHDL or Verilog. SystemVerilog? I haven’t used it much, but it feels like a vendor license trap to me (and it could totally be a C++ library). A Python test bench with cocotb? I’m definitely going to try this one. Let’s see if I’m right, wrong, or a bit of both.

4. DevOps

One of my biggest frustrations as an FPGA engineer:

“Theo! You forgot to do this again!!”

“No, we’ve always done this manually, over and over again, using the mouse on a GUI, and you’d better not mess up on the 10,000th time you do it.”

I ended up with tendinitis in my arm after that mission…

The DevOps part will be straightforward: GitLab, Docker, pipelines, Artifactory, etc., so that we can automate our workflow and enhance the quality of our projects.

5. Software

I was quite taken aback to discover that almost none of the FPGA engineers I’ve met possess software skills. Granted, I’ve only encountered a small subset of them, so perhaps I’ve just been unlucky. It’s no wonder that license vendors are taking advantage of us, given our inability to create our own tools.

While I’m not a software expert, I believe that basic Python and C skills are essential, at least for communicating effectively with my software colleagues.

I’m still unsure about what I’ll cover in this section. Should I go mainstream and study C/C++, which is widely used, or should I delve into Rust, which is more appealing to me but still relatively unknown in the field?

6. Open Source

Although I’ve listed it as the sixth point, it really should be a part of all the points above. It’s my engineering passion. I dream of a fully open-source/free software workflow that can be used in the industry, not just for personal projects. If I’m mistaken and it already exists, please let me know in the comments.

We’re certainly going to experiment with unconventional RTL languages like Chisel and Clash, among others. We’ll use Python cococtb for test benches, Yosys for synthesis and formal verification, and Verilator/GHDL for simulation. We’ll also try out NextPnR and Symbiflow.

7. How ?

How will I present all of this on my blog? Through articles about projects with code examples. From beginner projects (which are currently the only ones I feel capable of undertaking, haha) like interfaces and retro gaming, to advanced projects like a custom RISC-V that runs Linux.

If this journey interests you, please consider following LearnFpgaEasily on LinkedIn and Twitter, or bookmarking this page in your favorite browser.

Best regards,
Theophile Loubiere

Ps: I am a non-native English speaker, do not hesitate to correct (nicely) my spelling and grammar.
Ps2 : Thanks to River Saxton for the grammar and spelling correction.